Vernier Ring Based Pre-bond Through Silicon Vias Test in 3D ICs

Defects in TSV will lead to variations in the propagation delay of the net connected to the faulty TSV. A non-invasive Vernier Ring based method for TSV pre-bond testing is proposed to detect resistive open and leakage faults. TSVs are used as capacitive loads of their driving gates, then time interval compared with the fault-free TSVs will be detected. The time interval can be detected with picosecond level resolution, and digitized into a digital code to compare with an expected value of fault-free. Experiments on fault detection are presented through HSPICE simulations using realistic models for a 45 nm CMOS technology. The results show the effectiveness in the detection of time interval 10 ps, resistive open defects 0.2 kΩ above and equivalent leakage resistance less than 18 MΩ. Compared with existing methods, detection precision, area overhead, and test time are effectively improved, furthermore, the fault degree can be digitalized into digital code

In-Situ AlN Induced Valence State Variation of V in Vanadium Oxide Films Investigated by XPS

Vanadium oxide (VOx) thin films with and without in situ AlN layer were grown on single crystal sapphire substrates by pulsed laser deposition (PLD) with V2O5 target. The significant structure and morphology transforms resulted from the insertion of in-situ AlN layer were observed by X-ray diffraction (XRD) and field-emission scanning electron microscope (FESEM). To interpret the mechanism behind these phenomena, the valence state variation of vanadium (V) in VOx films induced by in-situ AlN layer was investigated by X-ray photoelectron spectroscopy (XPS) analyses. The results indicated that the valence state of V become more complicated and VOx films with the mixed V valence state of V5+,V4+and V3+ were obtained due to the introduction of AlN interfacial stress layer. Our achievements will be helpful for understanding the physical mechanism behind the exotic characteristics of VOx films induced by stress layer

Vernier ring based pre-bond through silicon vias test in 3D ICs

Defects in TSV will lead to variations in the propagation delay of the net connected to the faulty TSV. A non-invasive Vernier Ring based method for TSV pre-bond testing is proposed to detect resistive open and leakage faults. TSVs are used as capacitive loads of their driving gates, then time interval compared with the fault-free TSVs will be detected. The time interval can be detected with picosecond level resolution, and digitized into a digital code to compare with an expected value of fault-free. Experiments on fault detection are presented through HSPICE simulations using realistic models for a 45 nm CMOS technology. The results show the effectiveness in the detection of time interval 10 ps, resistive open defects 0.2 kΩ above and equivalent leakage resistance less than 18 MΩ. Compared with existing methods, detection precision, area overhead, and test time are effectively improved, furthermore, the fault degree can be digitalized into digital code